Module manager: Dr. Paul Steenson
Email: d.p.steenson@leeds.ac.uk
Taught: Semester 2 (Jan to Jun) View Timetable
Year running 2024/25
This module is not approved as a discovery module
To provide students with a knowledge, understanding and hands-on experience of VLSI design, primarily from a logic-circuit perspective, but including an introduction to contemporary VLSI chips, such as CPLDs and FPGAs, and the associated hierarchical and top-down (HDL) design methodologies leading to increasing complexity.
On completion of this module students should be able to:
1. Explain the principles of complex VLSI design and systems.
2. Describe combinational and sequential logic representations and their circuit implementation.
3. Explain the electrical properties of silicon logic, MOSFET, gate-level and switch-level elements of VLSI systems.
4. Use mathematical models to understand and implement design decisions and trade-offs.
5. Apply the principles of physical design, layout and modularisation to a VSLI design problems.
6. Use a CAD tool to analyse the behaviour of complex VLSI system blocks.
7. Explain the operation of memory devices and circuits, including the principles of architectural and system level design using interconnects, data flow and synchronisation.
Topics may include, but are not limited to:
Introduction to logic design. CMOS physical structure and relation to IC performance limitations
Electrical representation of MOSFETs and gate primitives. SPICE, switch-level and gate-level modelling
Design hierarchy and RTL modelling
Study of some key building blocks; CAD and evaluation
Data flow and routing: interconnect, bus, and clock distribution overview
Memory circuits; devices leading to programmable logic
| Delivery type | Number | Length hours | Student hours |
|---|---|---|---|
| Laboratory | 5 | 2 | 10 |
| Consultation | 5 | 1 | 5 |
| Examples Class | 4 | 1 | 4 |
| Lecture | 11 | 1 | 11 |
| Seminar | 2 | 1 | 2 |
| Independent online learning hours | 32 | ||
| Private study hours | 36 | ||
| Total Contact hours | 32 | ||
| Total hours (100hr per 10 credits) | 100 | ||
Students are expected to use private study time to consolidate their understanding of course materials, to undertake preparatory work for seminars, workshops, tutorials, examples classes and practical classes, and also to prepare for in-course and summative assessments.
Students studying ELEC modules will receive formative feedback in a variety of ways, including the use of self-test quizzes on Minerva, practice questions/worked examples and (where appropriate) through verbal interaction with teaching staff and/or post-graduate demonstrators.
| Assessment type | Notes | % of formal assessment |
|---|---|---|
| In-course Assessment | Coursework 1 | 30 |
| Total percentage (Assessment Coursework) | 30 | |
.Resits for ELEC and XJEL modules are subject to the School's Resit Policy and the Code of Practice on Assessment (CoPA), which are available on Minerva. Students should be aware that, for some modules, a resit may only be conducted on an internal basis (with tuition) in the next academic session.
| Exam type | Exam duration | % of formal assessment |
|---|---|---|
| Standard exam (closed essays, MCQs etc) | 3.0 Hrs 0 Mins | 70 |
| Total percentage (Assessment Exams) | 70 | |
Normally resits will be assessed by the same methodology as the first attempt, unless otherwise stated
There is no reading list for this module
Last updated: 7/31/2024
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