Module manager: Dr Craig Evans
Email: c.a.evans@leeds.ac.uk
Taught: Semesters 1 & 2 (Sep to Jun) View Timetable
Year running 2025/26
This module is not approved as a discovery module
In this module, students will study microprocessors and FPGAs. The module provides a deep insight into computer architectures. Starting from transistors, students will learn how to design their own computer and learn how to write computer programs in assembly language and binary machine code. The module is intended give students hands-on experience with industry-standard FPGA tools, enhancing their employability by developing practical skills in Verilog.
This module has the following objectives:
- To extend the learning of digital electronics.
- To develop knowledge in digital logic implementation from gate level combinational logic, all the way through to machine language and assembly instructions.
- To apply topics as a means of introducing programmable hardware, primarily FPGAs.
- To understand how to implement digital designs onto programmable hardware, as well as simulate and verify designs before and after implementation.
- To give students insight into various aspects of programmable hardware using industry standard tools and a bespoke development kit.
On successful completion of the module students will have demonstrated the following learning outcomes:
1. Apply appropriate computational and analytical techniques to model broadly-defined embedded systems problems.
2. Apply an integrated or systems approach to the solution of complex embedded systems problems.
3. Use practical laboratory and workshop skills to investigate broadly-defined embedded systems problems.
4. Communicate effectively on complex engineering matters with technical and non-technical audiences.
Skills Learning Outcomes
On successful completion of the module students will have demonstrated the following skills:
a) Application of computational and analytical techniques
b) Integrated systems approach
c) Practical and workshop skills
d) Communication
- Overview of the Hardware Description Language (HDL)
- Implementing logic gates in HDL
- Combinational logic: implementation of a binary adder and simple ALU (Arithmetic-Logic Unit) in HDL
- Sequential logic: flip-flop gates, registers and memory cells
- Design and implementation of a memory hierarchy in HDL
- Machine language: introduction of an instruction set in both binary and assembly language
- Composition of low-level assembly programs running them on a CPU emulator
- Computer architecture: integration of the previous designs into a model computer that executes machine code
- Assembler: how an assembler coverts the assembly language files into binary machine code
- HDL use in practical applications, specifically Verilog
- Comparison of the similarities of Verilog to the bespoke HDL language used
- Designing digital logic circuits in Quartus which are then programmed onto a custom FPGA platform
- Design of complex digital logic circuits, such as carry-lookahead adders and hardware multipliers, implemented in hardware and verified for speed compared to a microcontroller implementation
- Introduction to Modelsim as an industry-standard simulation tool, using it to simulate logic designs and confirm their validity before programming onto hardware
- Use of external peripherals such as switch inputs, potentiometers, LEDs and Seven Segment Displays to interface with the FPGA via GPIO and on-chip ADCs
| Delivery type | Number | Length hours | Student hours |
|---|---|---|---|
| Consultation | 8 | 1 | 8 |
| Lecture | 2 | 1 | 2 |
| Practical | 16 | 2 | 32 |
| Independent online learning hours | 30 | ||
| Private study hours | 128 | ||
| Total Contact hours | 42 | ||
| Total hours (100hr per 10 credits) | 200 | ||
Students studying ELEC modules will receive formative feedback in a variety of ways, including the use of self-test quizzes on Minerva, practice questions/worked examples and (where appropriate) through verbal interaction with teaching staff and/or post-graduate demonstrators.
| Assessment type | Notes | % of formal assessment |
|---|---|---|
| In-course Assessment | Class Test 1 | 25 |
| In-course Assessment | Coursework 1 | 25 |
| In-course Assessment | Coursework 2 | 50 |
| Total percentage (Assessment Coursework) | 100 | |
Resits for ELEC and XJEL modules are subject to the School's Resit Policy and the Code of Practice on Assessment (CoPA), which are available on Minerva. Students should be aware that, for some modules, a resit may only be conducted on an internal basis (with tuition) in the next academic session.
The reading list is available from the Library website
Last updated: 28/04/2025
Errors, omissions, failed links etc should be notified to the Catalogue Team